Modern microprocessors often employ a multi-level cache structure to expedite the reading and writing of data associated with the main system memory. Such multi-level cache structures are typically characterized by a hierarchy that includes a level-1 cache (L1), a level-2 cache (L2), and sometimes a level-3 cache (L3). In multi-core devices, the various cores may share one or more of these caches. For example, two cores may each have a single L1 cache, but might share a common L2 cache.
Many cache structures are inclusive—i.e., they are configured such that each higher-level cache (e.g., L2) also includes the data stored in the corresponding lower cache (e.g., L1). In such a case, the only scenario where the duplicated data in the higher-level cache does not cost significant overhead and improves performance is when the data in the lower-level cache is not valid and another processor that shares the same higher-level cache requests that data. However, it is known that this scenario rarely occurs in multi-core systems. As a result, inclusive multi-level cache structures typically require more chip space and consume more power than is necessary.